Two pins are used to supply power to the part; VSS is ground or 0 volts, while VCC is + 5.0 V ±5%
Sixteen pins are used to output address information from the MPU onto the address bus. When the processor does not require the bus for a data transfer, it will output address FFFFh, R/!W = 1, and BS = 0; this is a "dummy access" or !VMA cycle. All address bus drivers are made high-impedance when output bus available (BA) is high or when TSC is asserted. Each pin will drive one Schottky TTL load or four LS TTL loads and 90 pF.
These eight pins provide communication with the system bidirectional data bus. Each pin will drive one Schottky TTL load or four LS TTL loads and 130 pF.
This indicates the direction of data transfer on the data bus. A low indicates that the MPU is writing data onto the data bus. R/!W is made high impedance when BA is high or when TSC is asserted.
A low level on this Schrnitt-trigger input for greater than one bus cyde will reset the MPU, as shown in Figure 6. The reset vectors are fetched from locations FFFEh and FFFFh (Table 1) when interrupt acknowledge is true, (BA & BS = 1). During initial power on, the reset line should be held low until the clock input signals are fully operational.
Because the !RESET pin has a Schmitt-trigger input with a threshold voltage higher than that of standard peripherals, a simple R/C network may be used to reset the entire system. This higher threshold voltage ensures that all peripherals are out ot the reset state before the processor.
A low level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. When halted, the BA output is driven high indicating the buses are high impedance. BS is also high which indicates the processor is in the halt state. While halted, the MPU will not respond to external real-time requests (!FIRQ, !IRQ) although !NMI or !RESET will be latched for later response. During the halt state, Q and E should continue to run normally. A halted state (BA & BS = 1) can be achieved by pulling HALT low while !RESET is still low. See Figure 7.
The bus available output is an indication of an internal control signal which makes the MOS buses at the MPU high impedance. When BA goes low, a dead cycle will elapse before the MPU acquires the bus. BA will not be asserted when TSC is active, thus allowing dead cycle consistency. The bus status output signal, when decoded with BA, represents the MPU state (valid with leading edge of Q).
MPU
StateMPU State Definition BA BS 0 0 Normal (Running) 0 1 Interrupt or Reset Acknowledge 1 0 Sync Acknowledge 1 1 Halt Acknowledge
Interrupt Acknowledge is indicated during both cycles of a hardware vector fetch (!RESET, !NMI, !FIRQ, !IRQ, SWI, SWI2, SWI3). This signal, plus decoding of the lower four address lines, can provide the user with an indication of which interrupt level is being serviced and allow vectoring by device. See Table 1.
TABLE 1 - MEMORY MAP FOR INTERRUPT VECTORS
Address Interrupt Vector Description MS LS FFF0 FFF1 Reserved FFF2 FFF3 SWI3 FFF4 FFF5 SWI2 FFF6 FFF7 FIRQ FFF8 FFF9 IRQ FFFA FFFB SWI FFFC FFFD NMI FFFE FFFF RESET
Sync Acknowledge is indicated while the MPU is waiting for
external synchronization on an interrupt line.
Halt Acknowledge is indicated when the MC6809E is in a halt
condition.
A negative transition on this input requests that a non-maskable interrupt sequence be generated. A non-maskable interrupt cannot be inhibited by the program and also has a higher priority than !FIRO, !IRQ, or software interrupts. During recognition of an NMI, the entire machine state is saved on the hardware stack. After reset, an NMI will not be recognized until the first program load of the hardware stack pointer (S). The pulse width of !NMI low must be at least one E cycle. If the !NMI input does not meet the minimum set up with respect to Q, the interrupt will not be recognized until the next cycle See Figure 8.
A low level on this input pin will initiate a fast interrupt sequence, provided its mask bit (F) in the CC is clear This sequence has priority over the standard interrupt request (!IRQ) and is fast in the sense that it stacks only the contents at the condition code register and the program counter. The interrupt service routine should clear the source of the interrupt before doing an RTI. See Figure 9.
A low level input on this pin will initiate an interrupt request sequence provided the mask bit (l) in the CC is clear. Since !IRQ stacks the entire machine state, it provides a slower response to interrupts than !FIRQ. !IRQ also provides a lower priority than !FIRQ, Again, the interrupt service routine should clear the source of the interrupt before doing an RTI. See Figure 8.
E and Q are the clock signals required by the MC6809E. Q must lead E, that is, a transition on Q must be followed by a similar transition on E after a minimum delay. Addresses will be valid from the MPU, tAD after the falling edge of E, and data will be latched from the bus by the falling edge of E. While the Q input is fully TTL compatible, the E input directly drives internal MOS circuitry and, thus, requires a high level above normal TTL levels. This approach minimizes clock skew inherent with an internal buffer. Refer to BUS TIMING CHARACTERISTICS for E and Q and to Figure 10 which shows a simple clock generator for the MC6809E.
BUSY will be high for the read and modify cycles of a read-modify-write instruction and during the access of the first byte at a double-byte operation (e.g., LDX, STD, ADDD). BUSY is also high during the first byte of any indirect or other vector fetch (e.g., jump extended, SWI indirect, etc).
In a multiprocessor system, BUSY indicates the need to defer the rearbitration of the next bus cycle to insure the integrity of the above operations. This difference provides the indivisible memory access required tor a "test-and-set" primitive, using any one of several read-modify-write instructions.
BUSY does not become active during PSH or PUL operations. A typical read-modify-write instruction (ASL) is shown in Figure 11. Timing information is given in Figure 12. BUSY is valid tCD after the rising edge of Q.
AVMA is the advanced VMA signal and indicates that the MPU will use the bus in the following bus cycle. The predictive nature of the AVMA signal allows efficient shared-bus multiprocessor systems. AVMA is low when the MPU is in either a HALT or SYNC state. AVMA is valid tCD after the rising edge of Q.
LIC (last instruction cycle) is high during the last cycle of every instruction, and its transition from high to low will indicate that the first byte at an opcode will bc latched at the end of the present bus cycle. LIC will be high when the MPU is halted at the end of an instruction (i.e., not in CWAI, or RESET), in sync state, or while stacking during interrupts. LIC is valid tCD atter the rising edge of Q.
TSC (three-state control) will cause MOS address, data, and R/W buffers to assume a high-impedance state. The control signals (BA, BS, BUSY, AVMA, and LIC) will not go to the high-impedance state. TSC is intended to allow a single bus to be shared with other bus masters (processors or DMA controllers).
While E is low, TSC controls the address buffers and R/!W directly. The data bus buffers during a write operation are in a high-impedance state until Q rises at which time, if TSC is true, they will remain in a hiph-impedance state. If TSC is held beyond the rising edge of E, then it will be internally latched, keeping the bus drivers in a high-impedance state for the remainder ot the bus cycle. See Figure 13.
!FIRQ, and !IRQ requests are sampled on the falling edqe of Q. One cycle is required for synchronisation before these interrupts are recognised. The pending interrupts will not be serviced until completion of the current instruction unless a SYNC or CWAl instruction is present lf !IRQ and !FIRQ do not remain low until completion of the current instruction, they may not be recognised. However, !NMI is latched and need only remain low for one cycle. No interrupts are recognized or latched between the falling edge of end the rising edge of BS indicating !RESET acknowledge. See RESET sequence in the MPU flowchart in Figure 14.