--> | A11 | 1 | --6883-- --SAM-- |
40 | Vcc | |
--> | A10 | 2 | 39 | A12 | <-- | |
--> | A9 | 3 | 38 | A13 | <-- | |
--> | A8 | 4 | 37 | A14 | <-- | |
--> | X_IN | 5 | 36 | A15 | <-- | |
<-- | X_OUT | 6 | 35 | MA7 | --> | |
<-- | VCLK | 7 | 34 | MA6 | --> | |
--> | DA0 | 8 | 33 | MA5 | --> | |
--> | !HS | 9 | 32 | MA4 | --> | |
--> | !WE | 10 | 31 | MA3 | --> | |
<-- | !CAS | 11 | 30 | MA2 | --> | |
<-- | !RAS | 12 | 29 | MA1 | --> | |
<-- | Q | 13 | 28 | MA0 | --> | |
<-- | E | 14 | 27 | S0 | --> | |
--> | R/!W | 15 | 26 | S1 | --> | |
--> | A0 | 16 | 25 | S2 | --> | |
--> | A1 | 17 | 24 | A7 | <-- | |
--> | A2 | 18 | 23 | A6 | <-- | |
--> | A3 | 19 | 22 | A5 | <-- | |
Vss | 20 | 21 | A4 | <-- |
Pin directions not known for certain.
Approximate VHDL entity only!
entity 6883_SAM is port( a: in std_logic_vector(15 downto 0); -- address in ma: out std_logic_vector(7 downto 0); -- multiplexed address out s: out std_logic_vector(2 downto 0); -- decoded chip selects n_we: in std_logic; -- Not Write Enable n_hs: in std_logic; -- Horizontal Sync da0: in std_logic; -- video clock x_in: in std_logic; -- crystal osc sense (14.318180 MHz) x_out: out std_logic; -- crystal osc drive e: out std_logic; -- enabling clock q: out std_logic; -- quadrature clock n_ras: out std_logic; -- row address strobe n_cas: out std_logic; -- column address strobe vclk: out std_logic; -- video clock = crystal / 4 = (3.579545 MHz) ) end entity 6883_SAM;
d | c | b | a | E | Q | RAS | MUX | CAS | Action |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | /RAS strobes in row |
1 | 0 | MUX selects column | |||||||
1 | 0 | 0 | /CAS strobes in column | ||||||
1 | 0 | VDU accesses data | |||||||
1 | 0 | 0 | 1 | ||||||
1 | |||||||||
1 | 0 | 1 | |||||||
1 | 1 | ||||||||
1 | 0 | 0 | 0 | 1 | 1 | /RAS strobes in row | |||
1 | 0 | MUX selects column | |||||||
1 | 0 | 0 | /CAS strobes in column | ||||||
1 | 0 | 0 | CPU accesses data | ||||||
1 | 0 | 0 | |||||||
1 | |||||||||
1 | 0 | 1 | |||||||
1 | 0 | 1 |
a | 7.159090 MHz = crystal / 2 |
b | 3.579545 MHz = crystal / 4 = video clock. |
c | 1.787772 MHz = crystal / 8 |
d | 0.894886 MHz = crystal / 16 |
If you do not need the 3.579545 MHz signal for the 6847 VDG, then a 16MHz crystal would provide the full 1 MHz clock rate of a standard 6502. This would be a good character rate for a 6845 type controller, and 8MHz a good pixel clock rate.
The 6883 is not meant to run at 16MHz but if you are designing an equivalent then this should be easily achievable with modern components. A 32 MHz crystal would clock a 6502 at 2 MHz. At this frequency the duration of /RAS or /CAS low would be 5/32 microseconds = 156 nanoseconds.
The 2 MHz R65C02 requires a 60 ns data set up time so this would require DRAM with an access time (/CAS low to data valid) of 156-60 = 96.25 ns. You might be able to get away with 100ns rated parts!
If you used static RAM then timing is much simpler: The 6502 CLK2 selects video/CPU buses when low or high respectively. The 500ns cycle is split into two 250ns memory cycles, which allows the use of a commonly available 100ns 32Kx8 RAM chip. You can often find 32Kx8 RAM chips being used as cache RAM in old PC boards, rated at 15ns access times, which will be more than fast enough!
The 6883 was designed to work closely with the 6847 VDG, interleaving addresses from the latter. There are not enough pins to take the address lines from the 6847, so the 6883 simply duplicates them internally!