MOTOROLA SEMICONDUCTOR
TECHNICAL DATA
8-Bit Microprocessing Unit

The MC6809E is a high-performance 8-bit microprocessor which supports modern programming techniques such as position independence, re-entrancy, and modular programming.

This third-generation addition to the M6800 family has major architectural improvements, which include additional registers, instructions, and addressing modes.

The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The MC6809E has the most complete set of addressing modes available on any 8-bit microprocessor.

The MC6809E has hardware and software features which make it an ideal processor for higher level language execution or standard controller applications. External clock inputs are provided to allow synchronisation with peripherals, systems, or other MPUs.

MC6800 COMPATIBLE

Hardware - Interfaces with All M6800 Peripherals
Software - Upward Source Code Compatible Instruction Set and Addressing Modes

ARCHITECTURAL FEATURES

Two 16-Bit Index Registers
Two 16-Bit Indexable Stack Pointers
Two 8-Bit Accumulators can be Concatenated to Form One 16-Bit Accumulator
Direct Page Register Allows Direct Addressing Throughout Memory

HARDWARE FEATURES

External Clock Inputs, E and Q, Allows Synchronisation
TSC Input Controls Internal Bus Buffers
LIC Indicates Opcode Fetch
AVMA Allows Efficient Use of Common Resources in a Multiprocessor System
BUSY is a Status Line for Multiprocessing
Fast Interrupt Request Input Stacks Only Condition Code Register and Program Counter
Interrupt Acknowledge Output Allows Vectoring By Devices
Sync Acknowledge Output Allows for Synchronisation to External Event
Single Bus-Cycle !RESET
Single 5-Volt Supply Operation
NMI Inhibited After !RESET until After First Load of Stack Pointer
Early Address Valid Allows Use With Slower Memories
Early Write Data for Dynamic Memories

SOFTWARE FEATURES

10 Addressing Modes
- M6800 Upward Compatible Addressing Modes
- Direct Addressing Anywhere in Memory Map
- Long Relative Branches
- Program Counter Relative
- True Indirect Addressing
- Expanded Indexed Addressing
  0-, 5-, 8-, or 16-Bit Constant Offsets
  8- or 16-Bit Accumulator Offsets
  Auto-Increment Decrement by 1 or2
Improved Stack Manipulation
1464 Instruction with Unique Addressing Modes
8 x 8 Unsigned Multiply
16-Bit Arithmetic
Transfer Exchange All Registers
Push Pull Any Registers or Any Set of Registers
Load Effective Address

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MAXIMUM RATINGS

Symbol Value Unit

Supply Voltage V_CC -0.3 to +7.0 V

Input Voltage V_in -0.3 to +7.0 V

Operating Temperature Range
MC6809E, MC68A09E, MC68B09E
MC6809EC, MC68A09EC, MC68B09EC T_A T_L to T_H
0 to +70
-40 to +85 °C

Storage Temperature Range T_stg -56 to + 150 °C

This device contains circuitry to protect the inputs against damage due to static voltage or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e g., either V_SS or V_CC).

THERMAL CHARACTERISTICS

Thermal Resistance Symbol Value Unit

Cerdip H_JA 60 CW

Plastic 100

POWER CONSIDERATIONS

The average chip-junction temperature, T_J, in °C can be obtained from:

T_J = T_A + (P_D x Ø_JA ) (1)

where:

T_A = Ambient Temperature, °C
Ø_JA = Package Thermal Resistance, Junction-to-Ambient, °C W
P_D = P_INT+ P_PORT
P_INT = I_CC x V_CC, Watts - Chip Internal Power
P_PORT = Port Power Dissipation, Watts - User Determined

For most applications P_PORT < P_INT and can be neglected. P_PORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between P_D and T_J (if P_PORT is neglected) is:

P_D = K ÷ (T_J + 273 °C) (2)

Solving equations (1) and (2) for K gives:

K = P_D x (T_A + 273 °C) + Ø_JA x P_D² (3)

DC ELECTRICAL CHARACTERISTICS

(V_CC 5.0 V ± 5%, V_SS = 0 V DC. T_A = T_L to T_H unless otherwise noted).

CHARACTERISTIC		Symbol	Min	Typ	Max	Unit
Input High Voltage	Logic, Q	V_IH	V_SS + 2.0	-	V_CC	V
	!RESET	V_IHR	V_SS + 4.0	-	V_CC
	E	V_IHC	V_SS - 0.75	-	V_CC+0.3
Input Low Voltage	Logic, !RESET	V_IL	V_SS - 0.3	-	V_SS - 0.8	V V V
	E	V_ILC	V_SS - 0.3	-	V_SS - 0.4
	Q	V_ILQ	V_SS - 0.3	-	V_SS - 0.6
Input Leakage Current (V_IN = 0 to 5.25V, V_CC - max)	Logic, Q, !RESET	I_IN	-	-	2.5	µA
Input Leakage Current (V_IN = 0 to 5.25V, V_CC - max)	E	I_IN	-	-	100	µA
DC output high voltage	D0-7	V_OH	V_SS + 2.4	-	-	V
	A0-15, R/!W		V_SS + 2.4	-	-
	BA, BS, LIC, AVMA, BUSY		V_SS + 2.4	-	-
DC output low voltage (I_LOAD = 2.0 mA, V_CC = min)		V_OL	-	-	V_SS + 0.4	V
Internal Power Dissipation (measured at T_A = 0 °C in steady state operation)		P_INT			1.0	W
Capacitance (V_IN = 0V, T_A = 25°C, f = 1.0 MHz) Measured rather than 100% tested.	D0-7, Logic, Q, !RESET	C_IN	-	10	15	pf
	E	C_IN	-	30	50
	A0-15, R/!W, BA, BS, LIC, AVMA, BUSY	C_OUT	-	10	15
Frequency of Operation (E and Q inputs)	MC6809E	f	0.1	-	1.0	MHz
	MC68A09E		0.1	-	1.5
	MC68B09E		0.1	-	2.0
Hi-Z (off-state) input current, (V_IN = 0.4 to 2.4V, V_CC - max)	D0-7	I_TSI	-	2.0	10	µA
	A0-15, R/!W	I_TSI	-	-	100	µA

BUS TIMING CHARACTERISTICS (See Notes 1, 2, 3, and 4)

Ident. Number	Characteristics	Symbol	MC6809E		MC68A09E		MC68B09E		Unit
Ident. Number	Characteristics	Symbol	Min.	Max.	Min.	Max.	Min.	Max.	Unit
1	Cycle Time	T_CYC	1.0	10	0.667	10	0.5	10	µs
2	Pulse Width, E Low	PW_QH	450	9500	295	9500	210	9500	ns
3	Pulse Width, E High	PW_EH	450	9500	280	9500	220	9500	ns
4	Clock rise and fall time	t_r, t_f	-	25	-	25	-	25	ns
5	Pulse Width, Q High	PW_QH	450	9500	280	9500	220	9500	ns
7	Delay Time, E to Q Rise	t_EQ1	200	-	130	-	100	-	ns
7A	Delay Time, Q High to E Rise	t_EQ2	200	-	130	-	100	-	ns
7B	Delay Time, E High to Q Fall	t_EQ3	200	-	130	-	100	-	ns
7C	Delay Time, Q High to E Fall	t_EQ4	200	-	130	-	100	-	ns
9	Address Hold Time	t_AH	20	-	20		20	-	ns
11	Address Delay Time from E Low (BA, BS, R/!W)	t_DH	-	200	-	140	-	110	ns
17	Read Data Setup Time	t_DSR	80	-	60	-	40	-	ns
18	Read Data Hold Time	t_DHR	10	-	10	-	10	-	ns
20	Data Delay Time from Q	t_DDQ	-	200	-	140	-	110	ns
21	Write Data Hold Time	t_DHW	30	-	30	-	30	-	ns
29	Usable Access Tirne	t_ACC	695	-	440	-	330	-	ns
30	Control Delay Time	t_CD	-	300	-	250	-	200	ns
-	Interrupts, !HALT, !RESET and TSC Setup Time (Figures 6, 7, 8, 9, 12 and 13)	t_PCS	200	-	140	-	110	-	ns
-	TSC Dnve to Valid Logic Level	t_TSV	-	210	-	150	-	120	ns
-	TSC Release MOS Buffers to High Impedance (Figure 13)	t_TSR	-	200	-	140	-	110	ns
-	TSC Hi-Z Delay Time (Figure 13)	t_TSD	-	120	-	85	-	80	ns
-	Processor Control Rise and Fall Time (Figure 7)	t_PCSt_PCS	-	100	-	100	-	100	ns

FIGURE 1 - READ/WRITE DATA TO MEMORY OR PERIPHERALS TIMING DIAGRAM

NOTES.

Voltage levels shown are V_L <= 0.4 V, V_H >= 2.4 V, unIess otherwise specified
Measurement points shown are 0.8 V and 2.0 V, unIess otherwise specified
Hold time (9) for BA and BS is not specified.
Usable access time is computed by 1 - 4 -11 max - 17

FIGURE 2 - EXPANDED BLOCK DIAGRAM

	->					Buffers *	-->	A0-15

					<->	Buffers *	<->	D0-7
						v
	<->	PC		<->		Instruction register
	<--	U		<->		Instruction register
	<->	S		<->		v
	<--	Y		<->		Interrupt Control	<--	!RESET
	<--	X		<->			<--	!NMI
	<--	D{	A	<->			<--	!FIRQ
	<--	D{	B	<->			<--	!IRQ
	<--	DP	CC	<->		^ v
			v			Bus Control	-->	LIC
			ALU	<->			-->	AVMA
* Buffers are tristated by TSC							-->	R/!W
							<--	TSC
							<--	HALT
							-->	BA
						^ v
						Timing	<--	E
						Timing	<--	Q

FIGURE 3 - BUS TIMING TEST LOAD

C =  30 pf for BA, BS, LIC, AVMA, BUSY 
    130 pF for D0-7
     90 pF for A0-15, R/!W

R = 11.7 k for D0-7 
    18.5 k for A0-15. R/!W
    24   k for BA, BS, LIC, AVMA, BUSY

ORDERING INFORMATION

Package type

Frequency

Temperature range

Order number

Plastic P Suffix

1.0 MHz 
1.0 MHz 
1.5 MHz 
1.5 MHz 
2.0 MHz 
2.0 MHz

  0ºC to 70ºC 
-40ºC to 85ºC 
  0ºC to 70ºC 
-40ºC to 85ºC 
  0ºC to 70ºC 
-40ºC to 85ºC

MC6809EP 
MC6809ECP 
MC68A09EP 
MC68A09ECP 
MC68B09EP 
MC68B09ECP

Cerdip S Suffix

1.0 MHz 
1.0 MHz 
1.5 MHz 
1.5 MHz 
2.0 MHz 
2.0 MHz

  0ºC to 70ºC 
-40ºC to 85ºC 
  0ºC to 70ºC 
-40ºC to 85ºC 
  0ºC to 70ºC 
-40ºC to 85ºC

MC6809ES
MC6809ECS 
MC68A09ES 
MC68A09ECS 
MC68B09ES
MC68B09ECS

	Symbol	Value	Unit
Supply Voltage	V_CC	-0.3 to +7.0	V
Input Voltage	V_in	-0.3 to +7.0	V
Operating Temperature Range MC6809E, MC68A09E, MC68B09E MC6809EC, MC68A09EC, MC68B09EC	T_A	T_L to T_H 0 to +70 -40 to +85	°C
Storage Temperature Range	T_stg	-56 to + 150	°C

Thermal Resistance	Symbol	Value	Unit
Cerdip	H_JA	60	CW
Plastic	H_JA	100	CW

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Microprocessing Unit