| GND | 1 | U --6551-- |
28 | R/!W | <-- | |
| --> | CS0 | 2 | 27 | CLK | <-- | |
| --> | !CS1 | 3 | 26 | !IRQ | --> | |
| --> | !RST | 4 | 25 | D7 | <-> | |
| --> | RxC | 5 | 24 | D6 | <-> | |
| X1 | 6 | 23 | D5 | <-> | ||
| X0 | 7 | 22 | D4 | <-> | ||
| !RTS | 8 | 21 | D3 | <-> | ||
| !CTS | 9 | 20 | D2 | <-> | ||
| <-- | TxD | 10 | 19 | D1 | <-> | |
| !DTR | 11 | 18 | D0 | <-> | ||
| --> | RxD | 12 | 17 | !DSR | ||
| --> | RS0 | 13 | 16 | !DCD | ||
| --> | RS1 | 14 | 15 | VCC |
| Offset | ||
| 4 | Rd | Receive data |
| Wr | Transmit data | |
| 5 | Rd | Status |
| 6 | Rd/Wr | Control |
| 7 | Rd/Wr | Baud Generation |
Status Register
D7 D6 D5 D4 D3 D2 D1 D0 0 No Parity Error 1 Yes 0 No Framing Error 1 Yes 0 No Overrun 1 Yes 0 No RX data reg Full 1 Yes 0 No TX data reg Empty 1 Yes 0 high (N/A) DCD 1 low (N/A) 0 high (N/A) DSR 1 low (N/A) 0 No IRQ occurred 1 Yes
Control Register
D7 D6 D5 D4 D3 D2 D1 D0 0 DTR low (-12V) 1 DTR high (+12V) 0 IRQ enabled 1 IRQ disabled 0 TX IRQ disabled 1 TX IRQ enabled (bit3 must be 0 else disabled) 0 see bit 2 1 TX IRQ disabled transmit. BREAK on TXD if bit 2=1 0 Receiver normal mode 1 Receiver in echo mode (bits 2 & 3=0) 0 No parity 1 Parity enabled If bit 7=0: If bit 7=1: 0 Odd parity Mark bit sent (check dis) 1 Even parity Space bit sent (check dis) 0 Bit 6 is Parity 1 Bit 6 is Mark/Space sent
Baud Rate Generator Register
D7 D6 D5 D4 D3 D2 D1 D0 Baud Rate Divisor Baud Rate 0 1 1 0 300 0 1 1 1 600 1 0 0 0 1200 1 0 1 0 2400 1 0 1 1 3600 1 1 0 0 4800 1 1 1 0 9600 0 External clock(N/A) 1 Internal clock 0 0 WL=8 data bits 0 1 WL=7 data bits 1 0 WL=6 data bits 1 1 WL=5 data bits 0 1 stop bit 1 2 stop bits
1.5 stop bits (WL=5 & no parity)
1 stop bit (WL=8 and parity)