24 Assembler Mnemonics

The following section lists all the instruction mnemonics in alphabetical order. Each instruction is accompanied by a description of the instruction, a symbolic representation of the action performed by the instruction, a diagram showing the status-register flags affected by the instruction, and a list of the permitted addressing modes for the instruction.

The following symbols are used in this section:

Symbol: Definition:
+ Addition
- Subtraction
& Logical AND
\ Logical OR
: Logical Exclusive-OR
! Push onto hardware stack
^ Pull from hardware stack
= Assignment
M Memory location
(PC+1) Contents of location after op-code
@ Immediate addressing mode
~ No change to flag
% Change to flag
1 Set
0 Cleared
A Accumulator
X X Index Register
Y Y Index Register
PC Program Counter
PCH Low byte of Program Counter
PCL High byte of Program Counter
ADC Add memory to accumulator with carry
A,C=A+M+C		 ADC
N Z C I D V
% % % ~ ~ %
 
Addressing: Assembler format: Bytes: Cycles:
Immediate ADC @ Oper 2 2
Zero Page ADC Oper 2 3
Zero Page,X ADC Oper,X 2 4
Absolute ADC Oper 3 4
Absolute,X ADC Oper,X 3 4*
Absolute,Y ADC Oper,Y 3 4*
(Indirect,X) ADC (Oper,X) 2 6
(Indirect),Y ADC (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
AND AND memory with accumulator
A=A&M		 AND
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate AND @ Oper 2 2
Zero Page AND Oper 2 3
Zero Page,X AND Oper,X 2 4
Absolute AND Oper 3 4
Absolute,X AND Oper,X 3 4*
Absolute,Y AND Oper,Y 3 4*
(Indirect,X) AND (Oper,X) 2 6
(Indirect),Y AND (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
ASL Arithmetic shift left one bit (memory or accumulator)
C <-- 7 6 5 4 3 2 1 0 <-- 0
ASL
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Accumulator ASL A 1 2
Zero Page ASL Oper 2 5
Zero Page,X ASL Oper,X 2 6
Absolute ASL Oper 3 6
Absolute,X ASL Oper,X 3 7
 
BCC Branch if Carry Clear
Branch if C=0		 BCC
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BCC Oper 2 3*
* Add 1 if branch is to different page
 
BCS Branch if Carry Set
Branch if C=1		 BCS
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BCS Oper 2 3*
* Add 1 if branch is to different page
 
BEQ Branch if Carry Set
Branch if Z=1		 BEQ
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BEQ Oper 2 3*
* Add 1 if branch is to different page
 
BIT Test bits in memory with accumulator
A&M, N=M7, V=M6
Bit 6 and 7 are transferred to the status register. If the result of A&M is zero then Z=l, otherwise Z=0.		 BIT
N Z C I D V
M7% % ~ ~M6
 
Addressing: Assembler format: Bytes: Cycles:
Zero Page BIT Oper 2 3
Absolute BIT Oper 3 4
 
BMI Branch if result Minus
Branch if N=1		 BMI
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BMI Oper 2 3*
* Add 1 if branch is to different page
 
BNE Branch if result Not Equal to zero
Branch if Z=0		 BNE
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BNE Oper 2 3*
* Add 1 if branch is to different page
 
BPL Branch if result Plus
Branch if N=0		 BPL
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BEQ Oper 2 3*
* Add 1 if branch is to different page
 
BRK Force Break
Forced interrupt; PC+2 ! P !		 X
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied BRK Oper 1 7
A BRK command cannot be masked by setting I.
BCC Branch if Carry Clear
Branch if C=0		 BCC
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BCC Oper 2 3*
* Add 1 if branch is to different page
 
BVC Branch if Overflow Clear
Branch if V=0		 BVC
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BVC Oper 2 3*
* Add 1 if branch is to different page
 
BVS Branch if Overflow Set
Branch if Z=1		 BVS
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Relative BVS Oper 2 3*
* Add 1 if branch is to different page
 
CLC Clear Carry flag
C=0		 CLC
N Z C I D V
% % 0 ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLC   1 2
 
CLD Clear Decimal mode
D=0		 CLD
N Z C I D V
% % ~ ~ 0 ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLC   1 2
 
CLI Clear Interrupt disable bit
I=0		 CLI
N Z C I D V
% % ~ 0 ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLI   1 2
 
CLV Clear Overflow flag
V=0		 CLD
N Z C I D V
% % ~ ~ ~ 0
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLV   1 2
 
CMP Compare memory and accumulator
A-M		 CMP
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate CMP @ Oper 2 2
Zero Page CMP Oper 2 3
Zero Page,X CMP Oper,X 2 4
Absolute CMP Oper 3 4
Absolute,X CMP Oper,X 3 4*
Absolute,Y CMP Oper,Y 3 4*
(Indirect,X) CMP (Oper,X) 2 6
(Indirect),Y CMP (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
CPX Compare memory and index register X
X-M		 CPX
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate CPX @ Oper 2 2
Zero Page CPX Oper 2 3
Absolute CPX Oper 3 4
 
CPY Compare memory and index register Y
X-M		 CPY
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate CPY @ Oper 2 2
Zero Page CPY Oper 2 3
Absolute CPY Oper 3 4
 
DEC Decrement memory by one
M=M-1		 DEC
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Zero Page CMP Oper 2 5
Zero Page,X CMP Oper,X 2 6
Absolute CMP Oper 3 6
Absolute,X CMP Oper,X 3 7
 
DEX Decrement index register X by one
X=X-1		 DEX
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied DEX   1 2
 
DEY Decrement index register Y by one
Y=Y-1		 DEY
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLI   1 2
 
EOR Exclusive-OR memory with accumulator
A=A:M		 EOR
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate EOR @ Oper 2 2
Zero Page EOR Oper 2 3
Zero Page,X EOR Oper,X 2 4
Absolute EOR Oper 3 4
Absolute,X EOR Oper,X 3 4*
Absolute,Y EOR Oper,Y 3 4*
(Indirect,X) EOR (Oper,X) 2 6
(Indirect),Y EOR (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
INC Increment memory by one
M=M+1		 INC
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Zero Page INC Oper 2 5
Zero Page,X INC Oper,X 2 6
Absolute INC Oper 3 6
Absolute,X INC Oper,X 3 7
 
INX Increment index register X by one
X=X+1		 INX
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied INX   1 2
 
INY Increment index register Y by one
X=X+1		 INY
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied INY   1 2
 
JMP Jump to new location
PCL=(PC+1), PCH=(PC+2)		 JMP
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Absolute JMP Oper 3 3
Indirect JMP (Oper) 3 5
 
JSR Jump to Subroutine saving return address
PC+2 !, PCL=(PC+1), PCH=(PC+2)		 JSR
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Absolute JSR Oper 3 6
 
LDA Load accumulator with memory
A=M		 LDA
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate LDA @ Oper 2 2
Zero Page LDA Oper 2 3
Zero Page,X LDA Oper,X 2 4
Absolute LDA Oper 3 4
Absolute,X LDA Oper,X 3 4*
Absolute,Y LDA Oper,Y 3 4*
(Indirect,X) LDA (Oper,X) 2 6
(Indirect),Y LDA (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
LDX Load index register X with memory
X=M		 LDX
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate LDX @ Oper 2 2
Zero Page LDX Oper 2 3
Zero Page,Y LDX Oper,Y 2 4
Absolute LDX Oper 3 4
Absolute,Y LDX Oper,Y 3 4*
* Add 1 if page boundary crossed.
 
LDY Load index register Y with memory
Y=M		 LDY
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate LDY @ Oper 2 2
Zero Page LDY Oper 2 3
Zero Page,X LDY Oper,X 2 4
Absolute LDY Oper 3 4
Absolute,X LDY Oper,X 3 4*
* Add 1 if page boundary crossed.
 
LSR Logical shift right one bit (memory or accumulator)
0 --> 7 6 5 4 3 2 1 0 --> C
LSR
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Accumulator LSR A 1 2
Zero Page LSR Oper 2 5
Zero Page,X LSR Oper,X 2 6
Absolute LSR Oper 3 6
Absolute,X LSR Oper,X 3 7
 
NOP No Operation NOP
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied NOP   1 2
 
ORA Load accumulator with memory
A=A\M		 ORA
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Immediate ORA @ Oper 2 2
Zero Page ORA Oper 2 3
Zero Page,X ORA Oper,X 2 4
Absolute ORA Oper 3 4
Absolute,X ORA Oper,X 3 4*
Absolute,Y ORA Oper,Y 3 4*
(Indirect,X) ORA (Oper,X) 2 6
(Indirect),Y ORA (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
PHA Push Accumulator to stack
A !		 PHA
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied PHA   1 3
 
PHP Push Processor status to stack
=		 PHP
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied PH   1 3
 
PLA Pull Accumulator from stack
A ^		 PLA
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied PH   1 4
 
PLP Pull Processor status from stack
P ^		 PLP
N Z C I D V
from stack
 
Addressing: Assembler format: Bytes: Cycles:
Implied PH   1 4
 
ROL Rotate Left one bit (memory or accumulator)
+ -- 7 6 5 4 3 2 1 0 <-- C
+ -- -- -- -- -- -- -- -- -- --- +
ROL
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Accumulator ROL A 1 2
Zero Page ROL Oper 2 5
Zero Page,X ROL Oper,X 2 6
Absolute ROL Oper 3 6
Absolute,X ROL Oper,X 3 7
 
ROR Rotate right one bit (memory or accumulator)
C --> 7 6 5 4 3 2 1 0 --+  
+ --- -- -- -- -- -- -- -- -- --+  
ROR
N Z C I D V
% % % ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Accumulator ROR A 1 2
Zero Page ROR Oper 2 5
Zero Page,X ROR Oper,X 2 6
Absolute ROR Oper 3 6
Absolute,X ROR Oper,X 3 7
 
RTI Return from Interrupt
P^ PC^		 RTI
N Z C I D V
From stack
 
Addressing: Assembler format: Bytes: Cycles:
Implied RTI   1 6
 
RTS Return from Subroutine
P^ PC^		 RTS
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied RTS   1 6
 
SBC Subtract memory from accumulator with carry
A,C=A-M-(C-1)		 SBC
N Z C I D V
% % % ~ ~ %
 
Addressing: Assembler format: Bytes: Cycles:
Immediate SBC @ Oper 2 2
Zero Page SBC Oper 2 3
Zero Page,X SBC Oper,X 2 4
Absolute SBC Oper 3 4
Absolute,X SBC Oper,X 3 4*
Absolute,Y SBC Oper,Y 3 4*
(Indirect,X) SBC (Oper,X) 2 6
(Indirect),Y SBC (Oper),Y 2 5*
* Add 1 if page boundary crossed.
 
SEC Set Carry flag
C=1		 SEC
N Z C I D V
% % 1 ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLC   1 2
 
SED Set Decimal mode
D=1		 SED
N Z C I D V
% % ~ ~ 1 ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLC   1 2
 
SEI Set Interrupt disable bit
I=1		 SEI
N Z C I D V
% % ~ 1 ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied CLI   1 2
 
STA Store accumulator in memory
M=A		 STA
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Zero Page STA Oper 2 3
Zero Page,X STA Oper,X 2 4
Absolute STA Oper 3 4
Absolute,X STA Oper,X 3 5
Absolute,Y STA Oper,Y 3 5
(Indirect,X) STA (Oper,X) 2 6
(Indirect),Y STA (Oper),Y 2 6
* Add 1 if page boundary crossed.
 
STX Store index register X in memory
M=X		 STX
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Zero Page STX Oper 2 3
Zero Page,Y STX Oper,Y 2 4
Absolute STX Oper 3 4
 
STY Store index register Y in memory
M=Y		 STY
N Z C I D V
~ ~ ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Zero Page STY Oper 2 3
Zero Page,X STY Oper,X 2 4
Absolute STY Oper 3 4
 
TAX Transfer Accumulator to index register X
X=A		 TAX
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied TAX   1 2
 
TAY Transfer Accumulator to index register Y
Y=A		 TAY
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied TAY   1 2
 
TSX Transfer Stack pointer to index register X
X=S		 TSX
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied TSX   1 2
 
TXA Transfer index register X to Accumulator
A=X		 TXA
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied TXA   1 2
 
TXS Transfer index register X to stack pointer
S=X		 TXS
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied TXS   1 2
 
TYA Transfer index register Y to Accumulator
A=Y		 TYA
N Z C I D V
% % ~ ~ ~ ~
 
Addressing: Assembler format: Bytes: Cycles:
Implied TYA   1 2
 

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