Atom 6522 Input/Output
Copied from http://www.howell1964.freeserve.co.uk/parts/parts.htm

     

Layout

     
  Vss 1 U










  6522 VIA  
40 ca1 <--
<-> pa0 2 39 ca2 <--
<-> pa1 3 38 rs0 <--
<-> pa2 4 37 rs1 <--
<-> pa3 5 36 rs2 <--
<-> pa4 6 35 rs3 <--
<-> pa5 7 34 !rst <--
<-> pa6 8 33 d0 <->
<-> pa7 9 32 d1 <->
<-> pb0 10 31 d2 <->
<-> pb1 11 30 d3 <->
<-> pb2 12 29 d4 <->
<-> pb3 13 28 d5 <->
<-> pb4 14 27 d6 <->
<-> pb5 15 26 d7 <->
<-> pb6 16 25 ph2 <--
<-> pb7 17 24 cs1 <--
<-> cb1 18 23 !cs2 <--
<-> cb2 19 22 r/!w <--
  Vcc 20 21 !irq <--
         


Offset Register

00 Data register B
01 Data register A
02 Data register B
03 Data register A
04 Timer 1 low counter / latch
05 Timer 1 high counter
06 Timer 1 low latch
07 Timer 1 high latch
08 Timer 2 low counter / latch
09 Timer 2 high counter
0A Shift register
0B Auxiliary control register
0C Peripheral control register
0D Interrupt flag register
0E Interrupt enable register
0F Data register A

Address = Base + Offset
Base == B800 in Atom mode.
Base == 7800 in BBC Micro mode.


Hardware structure

Approximate VHDL entity only!

entity VIA_6522 is	--
port(
	n_rst:	in	std_logic;	-- Reset
	n_wr:	in	std_logic;	-- Read / Not Write
	ph2:	in	std_logic;	-- CPU clock phase 2
	cs1:	in	std_logic;
	n_cs2:	in	std_logic;
	rs:	in	std_logic_vector(3 downto 0);
	d:	inout	std_logic_vector(7 downto 0);
	pa:	inout	std_logic_vector(7 downto 0);	-- Port A
	ca:	inout	std_logic_vector(2 downto 1);	-- Port CA
	pb:	inout	std_logic_vector(7 downto 0);	-- Port B
	cb:	inout	std_logic_vector(2 downto 1);	-- Port CB
	);
end entity VIA_6522;

Pinout comparison:
Pin 6821
6520
6522 6526
18 CB1 CB1 !PC
19 CB2 CB2 TOD in
21 R/!W !IRQ !IRQ
22 CS0 R/!W R/!W
23 !CS2 !CS2 !CS
24 CS1 CS1 !FLAG
35 A0 RS3 RS3
36 A1 RS2 RS2
37 !IRQB RS1 RS1
38 !IRQA RS0 RS0
39 CA2 CA2 SP
40 CA1 CA1 CNT